As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 19, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.
In order to properly accomplish such tasks, the computer system 10 relies on the basis of time to coordinate its various operations. To this end, a crystal oscillator 18 generates a system clock signal sys_clk (also referred to in the art as xe2x80x9creference clockxe2x80x9d) to various parts of the computer system 10. However, modern microprocessors and other integrated circuits typically operate at frequencies significantly higher than that of the signals most crystal oscillators can provide, and accordingly, designers often implement various techniques to increase or multiply the frequency of the system clock signal to particular computer system components.
For example, as shown in FIG. 1, because the microprocessor 12 is able to operate at frequencies higher than that of the system clock signal sys_clk, a phase locked loop 22 is often used to output a chip clock signal chip_clk to the microprocessor 12, in which case, the chip clock signal chip_clk has a frequency that is significantly higher than that of the system clock signal sys_clk. However, in some circumstances, although frequency multiplication may be needed, implementation of a complex clock generator, such as the phase locked loop 22 shown in FIG. 1, may prove to be difficult or too costly in terms of space and design time.
To this end, integrated circuit designers have implemented various simpler frequency multiplier designs, one of which is shown in FIG. 2. In FIG. 2, an exclusive-OR gate 30 has a first input 32 operatively connected to a first clock signal clk_in and an output 34 operatively connected to a second clock signal clk_out. A delay chain 38 formed by a series inverters 40 has an input 42 operatively connected to the first clock signal clk_in and an output operatively connected to a second input 44 of the exclusive-OR gate 30.
FIG. 3 shows a timing diagram in accordance with the typical frequency multiplier design shown in FIG. 2. The timing diagram shows clock waveforms for the first clock signal clk_in (at the first input 32 of the exclusive-OR gate 30 shown in FIG. 2), the second input 44 of the exclusive-OR gate 30 shown in FIG. 2, and the second clock signal clk_out (at the output 34 of the exclusive-OR gate 30 shown in FIG. 2).
As shown in FIG. 3, the clock waveform at the second input 44 is delayed with respect to the clock waveform of the first input 32 (due to the delay of the delay chain 38 shown in FIG. 2). Because the exclusive-OR gate 30 outputs xe2x80x98highxe2x80x99 when its inputs are different, and because the clock waveforms at the first input 32 and the second input 44 are different after each rising and falling edge for a period of time less than half a clock waveform cycle at the first input 32 (and at the second input 44), the clock waveform for the output 34 of the exclusive-OR gate 30, i.e., the second clock signal clk_out, has a frequency twice that of the first clock signal clk_in.
According to one aspect of the present invention, an integrated circuit comprises: an input stage arranged to receive an input clock signal; a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal; a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal; and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.
According to another aspect, an integrated circuit comprises: means for inputting an input clock signal; first means for generating a low pulse on a first signal dependent on a low phase of the input clock signal; second means for generating a low pulse on a second signal dependent on a high phase of the input clock signal; and means for outputting a high pulse on an output clock signal for every low pulse on the first signal and the second signal.
According to another aspect, a method for multiplying a clock frequency comprises: inputting an input clock signal; generating a low pulse on a first signal dependent on a low phase of the input clock signal; generating a low pulse on a second signal dependent on a high phase of the input clock signal; and outputting a high pulse on an output clock signal for every low pulse on the first signal and the second signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.